Defects in integrated circuits can result in circuits that do not meet the required specifications. These defects can be caused through the manufacturing process and/or can arise over time. Moreover, these defects can result in hard failures or catastrophic faults, e.g., short circuits or open circuits, or can manifest themselves as subtle changes in electrical operation or parametric faults, e.g., increased current leakage or changes in circuit timing.
In integrated circuits, shifts of threshold voltages (Vt) over the lifetime of the chip can result in system failures. Parts of the integrated circuit, such as devices and circuits to be measured, are conventionally designed according to a modeled predetermined shift. However, some parts will shift more than the modeled shift over the lifetime of the part.
If the actual shift for parts could be measured, such parts could be replaced before the system fails. However, there is no conventional method to measure in system and/or to provide early warning of system fail. Thus, there exists no conventional manner for addressing potential fails with preventative maintenance.
Further, conventional reliability assessment techniques in integrated circuits generally require extensive measurement and stress of many different circuits. According to these techniques, semiconductor products being tested are first measured to ascertain a set of functional criteria for the chip and thereafter the semiconductor products are stressed and then remeasured. The measured data is evaluated to empirically determine both fail rate and to predict reliability.
The above-discussed conventional techniques depend on empirical validation. In particular, in order to identify the separate parametric, e.g., current or threshold voltage, and defect, e.g., particle, contribution under conventional techniques, failure analysis is required. Moreover, the ability to measure parametric variation according to the conventional techniques is limited.
Further, the conventional techniques are merely representative of problems. In this regard, because structures used to measure parametric variation are not cycled during stress, these structures are not representative of stressed circuits. Still further, according to the conventional techniques, the impact of different layout environments on layout cannot be assessed.